(1) Technical Field
This invention generally relates to electronic power supplies, and more specifically to capacitive energy transfer DC-to-DC converters (DC/DC converters), such as charge pumps.
(2) Background
DC/DC converter power supply circuits provide a DC output voltage based upon a DC source voltage, where the output voltage is typically different than the input voltage. As the term is used herein, DC/DC converters do not encompass voltage reduction regulator circuits that use a linear pass device, but rather involve energy transfer from input to output through an energy storage device, such as a capacitor or an inductor.
A type of DC/DC converter is a “charge pump”, which obtains energy for the output voltage primarily by means of capacitive transfer from the source to the output. Energy transfer capacitors used in charge pumps are typically known as “fly capacitors” or “fly caps”. An inductor is not generally the primary energy transfer device in a charge pump, though of course hybrid devices are possible that employ inductive energy transfer in addition to capacitive energy transfer. A charge pump may derive an output voltage that is higher than a source voltage, or that is inverted from a source voltage, or that is referenced to a different voltage than the source voltage, and may do all of these things concurrently.
Charge pumps may be implemented for a wide variety of purposes. They are well suited for integrated circuit fabrication because the devices and elements required are compatible with most integrated circuit fabrication techniques. For example, a charge pump may be employed to generate a negative gate bias supply for an integrated circuit that switches an antenna between send and receive circuitry of a transceiver, as shown in FIG. 1. Many wireless transceivers, such as cellular telephones, employ a single antenna for both receiving and transmitting. While such systems are receiving, an antenna 102 must be coupled to receive circuitry 103 that may further include, for example, a filter 104 and a low noise amplifier 106, to provide the received signal for further processing. However, while such systems are transmitting, the antenna 102 must be disconnected from the sensitive receive circuitry 103 and coupled instead to relatively high power transmit circuitry 107. The transmit circuitry 107 may further include, for example, a power amplifier 108 and a transmit filter 110 to process a transmit signal. Note that the circuit shown in FIG. 1 is schematically simple for ease of understanding; in an actual implementation, there are often multiple transmit and receive circuits, and transmission and reception may be occurring on the same path at the same time.
A radio frequency (RF) switch 112 may be used to perform such antenna switching functions, as well as RF switching functions in general. Ideally, such switches may be integrated together with the receive and/or transmit circuitry, and in any event are desirably very small, due to integrated circuit die cost and space limitations in portable transceivers such as mobile telephones and handy talkies. In order to achieve good performance from switching devices, such as FETs, used to implement such RF switches, many designs need a special bias supply that extends negatively below the supply rails of the transmit and receive circuitry, such as a −3V supply. In view of the space and cost constraints of transceiver units such as mobile telephones, a charge pump is particularly suitable for generating such a bias supply because it can be readily integrated into a very small circuit and requires only a single external voltage supply, eliminating the need for multiple power supplies.
Fully-integrated charge pump based power supplies can be both electrically noisy and weak (i.e., not able to drive large load currents). The output drive strength is related to the frequency of the clock source driving the charge pump, and the size of the capacitors used to shuttle charge to a new voltage level. A higher clock frequency will improve the output drive strength but can allow for more noise coupling into the RF path. In particular, the frequency of the charge pump clock can show up as a distinct spur both at multiples of itself in baseband frequencies and/or at multiples of itself offset from whatever RF frequency is being utilized by a particular system. In the case of a switch with both transmit and receive signals present in different bands, it is possible for clock spurs offset from the transmit band to show up in the receive band. Thus it is desirable to use lower clock frequencies for charge pump circuits.
Using larger capacitors also improves drive strength of the charge pump, but doing so can consume a significant amount of integrated circuit chip area, and the more chip area that is used, the more coupling area there is to the RF path. Thus, there are trade-offs to be made to get to an optimal design for charge pump circuits used in a particular system.
In a simple single-stage charge pump, one capacitor is used as a “fly” capacitor, and one capacitor is used for a storage capacitor. The fly capacitor will alternately charge to some supply voltage +Vdd and then be switched to some other location to discharge into the “pumped” voltage supply, which is the new voltage supply being generated. In a simple negative charge pump example, the fly capacitor would be charged to Vdd relative to ground on one phase of a clock signal, and then on the other phase of the clock signal, the positive terminal would be tied to ground and the negative terminal to a storage capacitor to provide an output node Vss; this would charge Vss to be at −Vdd (thus the example circuit is a negative voltage “pumped” power supply; positive voltage charge pumps are equally well known in the art).
FIG. 2a is a schematic circuit diagram showing a prior art single-stage charge pump. FIG. 2b is a timing diagram of a two-phase clock signal 200 used in conjunction with the circuit shown in FIG. 2a. During phase 1 of the clock signal 200, switches 202 and 204 are closed and switches 208 and 210 are open, thereby coupling the positive terminal of the fly capacitor Cfly 206 to a supply voltage Vdd and the negative terminal to ground, thus charging Cfly to Vdd. During phase 2 of the clock signal 200, switches 202 and 204 are open and switches 208 and 210 are closed, thereby coupling the positive terminal of the fly capacitor Cfly 206 to ground and the negative terminal to a storage capacitor Cstorage1 212, thus charging Cstorage1 toward −Vdd. An output node Vss 214 provides the desired negative voltage “pumped” power supply, at approximately −Vdd.
The size of the storage capacitor used in charge pumps is generally determined by how much clock noise can be tolerated on the resulting pumped supply to a particular system. Typically, the storage capacitor has to be much larger than the fly capacitor. As such, to get an electrically quiet output, large amounts of capacitor area are required on an integrated circuit.
For two stage charge pumps, the problem gets compounded. A two-stage charge pump would for instance be used to create a supply of −2 Vdd or +3 Vdd. Two fly caps and two storage capacitors are required. The drive efficiency of the charge is reduced in half while the area required by all the capacitors is doubled, assuming each individual capacitor stays the same value. It could further be shown that higher stage count charge pumps are even worse off.
FIG. 3a is a schematic circuit diagram showing a prior art two-stage charge pump. FIG. 3b is a timing diagram of a two-phase clock signal 300 used in conjunction with the circuit shown in FIG. 3a. During phase 1 of the clock signal 300, switches 302, 304, and 306 are closed and switches 308, 310, and 312 are open, thereby coupling the positive terminal of fly capacitor Cfly1 314 to a supply voltage Vdd and its negative terminal to ground, thus charging Cfly1 314 to Vdd. During the same clock phase, the positive terminal of fly capacitor Cfly2 316 is coupled to ground and its negative terminal is coupled to a storage capacitor Cstorage1 318, thus charging the negative terminal of Cfly2 316 toward −Vdd (Cstorage1 318 having been charged toward −Vdd by Cfly1 314 on previous cycles).
During phase 2 of the clock signal 300, switches 302, 304, and 306 are open and switches 308, 310, and 312 are closed, thereby coupling the positive terminal of Cfly1 to ground and its negative terminal to Cstorage1 318, thus charging Cstorage1 318 toward −Vdd. During the same clock phase, the positive terminal of Cfly2 is coupled to storage capacitor Cstorage1 and the negative terminal of Cfly2 is coupled to a storage capacitor Cstorage2 320, thus charging Cstorage2 toward −2 Vdd. An output node Vss 322 provides the desired negative voltage “pumped” power supply, at approximately −2 Vdd.
The switches shown in FIG. 2a and FIG. 3a may be, for example, field effect transistors (FETs) selected from the many variants available, such as IGFETs, MOSFETs, and the like. The various capacitors shown in these figures may be implemented in known manner.
The method and apparatus presented below address this need for a low-noise charge pump. Various aspects of the method and apparatus described below will be seen to provide further advantages, as well, for the design and construction of charge pumps that are relatively free of noise spurs.